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3-149 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 general description the tc820 is a 3-3/4 digit, multi-measurement system especially suited for use in portable instruments. it inte- grates a dual slope a/d converter, auto-ranging frequency counter and logic probe into a single 44-pin surface mount or 40-pin through hole package. the tc820 operates from a single 9v input voltage (battery) and features a built-in battery low flag. function and decimal point selection are accomplished with simple logic inputs designed for direct connection to an external microcontroller or rotary switch. ease of use, low power operation and high functional integration make the tc820 desirable in a variety of analog measurement applications. 3-3/4 digit a/d converter with frequency counter and logic probe features n multiple analog measurement system digit a/d converter frequency counter logic probe n low noise a/d converter: differential inputs, (1pa bias current) on-chip 50ppm/ c voltage reference n frequency counter: 4mhz maximum input frequency auto-ranging over four decade range n logic probe: two lcd annunciators buzzer driver n 3-3/4 digit display with overrange indicator n lcd display driver with built-in contrast control n data hold input for comparison measurements n low battery detect with lcd annunciator n underrange and overrange outputs n on-chip buzzer driver with control input n 44-pin plastic flat pack or plcc or 40-pin plastic dip packages peak hold comparator 3-3/4 digit a/d converter low battery detect decimal point drivers buzzer driver function select logic probe autoranging frequency counter clock oscillator triple lcd drivers low drift voltage differential reference logic high logic low overrange pkhold low batt annunciator drive decimal point select buzzer control function select digital ground to lcd and buzzer peak hold logic probe input frequency input full-scale select underrange overrange analog gnd volts frequency logic triplex lcd 9v tc820 analog input + eoc functional block diagram ordering information temperature part no. resolution package range tc820ckw 3-3/4 digits 44-pin plastic 0 c to +70 c quad flat package TC820CLW 3-3/4 digits 44-pin plastic 0 c to +70 c leadless chip carrier tc820cpl 3-3/4 digits 40-pin plastic dip 0 c to +70 c tc820-10 10/17/96 tc820
3-150 telcom semiconductor, inc. 3-3/4 digit a/d converter with frequency and logic probe tc820 a "peak reading hold" input allows the tc820 to retain the highest a/d or frequency reading. this feature is useful in measuring motor starting current, maximum tempera- ture, and similar applications. a family of instruments can be created with the tc820. no additional design effort is required to create instruments with 3-3/4 digit resolution. the tc820 operates from a single 9v battery, with typical power of 10 mw. packages include a 40-pin plastic dip, 44-pin plastic flat package, and 44-pin plcc. competitive evaluation features comparison tc820 7106 3-3/4 digit resolution yes no auto-ranging frequency counter yes no logic probe yes no decimal point drive yes no peak reading hold yes no (frequency or voltage) display hold yes no simple 10:1 range change yes no buzzer drive yes no low battery detection yes no with annunciator overrange detection yes no with annunciator low drift reference yes no underrange/overrange yes no logic output input overload display "ol" "1" lcd annunciator driver yes no lcd drive type triplexed direct lcd pin connections 15 24 lcd elements 36 23 general description the tc820 is a 3-3/4 digit measurement system com- bining an integrating analog-to-digital converter, frequency counter, and logic level tester in a single package. the tc820 supersedes the tc7106 in new designs by improv- ing performance and reducing system cost. the tc820 adds features that are difficult, expensive, or impossible to provide with older a/d converters (see the competitive evaluation). the high level of integration permits tc820- based instruments to deliver higher performance and more features, while actually reducing parts count. fabricated in low-power cmos, the tc820 directly drives a 3-3/4 digit (3999 maximum) lcd. with a maximum range of 3999 counts, the tc820 provides 10 times greater resolution in the 200mv to 400mv range than traditional 3-1/2 digit meters. an auto-zero cycle guarantees a zero reading with a 0v input. cmos process- ing reduces analog input bias current to only 1pa. rollover error (the difference in readings for equal magnitude but opposite polarity input signals) is less than 1 count. differ- ential reference inputs permit ratiometric measurements for ohms or bridge transducer applications. the tc820's frequency counter option simplifies design of an instrument well-suited to both analog and digital troubleshooting: voltage, current, and resistance measure- ments, plus precise frequency measurements to 4mhz (higher frequencies can be measured with an external prescaler), and a simple logic probe. the frequency counter will automatically adjust its range to match the input fre- quency, over a four-decade range. two logic level measurement inputs permit a tc820- based meter to function as a logic probe. when combined with external level shifters, the tc820 will display logic levels on the lcd and also turn on a piezoelectric buzzer when the measured logic level is low. other tc820 features simplify instrument design and reduce parts count. on-chip decimal point drivers are in- cluded, as is a low battery detection annunciator. a piezo- electric buzzer can be controlled with an external switch or by the logic probe inputs. two oscillator options are pro- vided: a crystal can be used if high accuracy frequency measurements are desired, or a simple rc option can be used for low-end instruments.
3-151 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 electrical characteristics: v s = 9v, t a = 25 c, unless otherwise specified. symbol parameter test conditions min typ max units zero input reading v in = 0v C 000 000 +000 digital full scale = 400 mv reading re roll-over error v in = 390mv C 1 0.2 +1 counts full-scale = 400mv nl nonlinearity (maximum full-scale = 400mv C 1 0.2 +1 count deviation from best straight line fit) ratiometric reading v in = v ref , tc820 1999 1999/2000 2000 digital cmrr common-mode rejection v cm = 1v, v in = 0v 50 m v/v ratio full-scale = 400mv (v fs = 200 mv) vcmr common-mode voltage input high, input low v ss + 1.5 v dd C 1 v range e n noise (p-p value not v in = 0v 15 m v exceeded 95% of time) full-scale = 400mv i in input leakage current v in = 0v t a = 25 c110pa 0 c t a +70 c20 C 40 c t a +85 c 100 v com analog common voltage 25 k w between common and v dd (v ss C v com ) 3.15 3.3 3.45 v v ctc common voltage 25 k w between common and v dd temperature coefficient 0 c t a +70 c 35 50 ppm/ c C 40 c t a +85 c50 tc zs zero reading drift v in = 0v 0 c t a +70 c 0.2 m v/ c C 40 c t a +85 c1 tc fs scale factor v in = 399mv temperature coefficient 0 c t a +70 c 1 5 ppm/ c C 40 c t a +85 c5 ext ref = 0 ppm/ c i s supply current v in = 0v 1 1.5 ma peak-to-peak backplane v s = 9v 4.25 4.7 5.3 v drive voltage v disp = dgnd absolute maximum ratings* supply voltage (v dd to gnd) .....................................15v analog input voltage (either input) (note 1) .... v dd to v ss reference input voltage (either input) ............. v dd to v ss digital inputs ............................................... v dd to dgnd v disp ............................................. v dd to (dgnd C 0.3v) package power dissipation (t a 70 c) (note 2) 40-pin plastic dip ............................................. 1.23w 44-pin plcc .....................................................1.23w 44-pin plastic flat package .............................. 1.00w operating temperature range "c" devices ............................................ 0 c to +70 c "e" devices ....................................... C 40 c to +85 c storage temperature range ................ C 65 c to +150 c lead temperature (soldering, 10 sec) ................... 300 c * static-sensitive devices. unused devices should be stored in conductive material to protect against static discharge and static fields. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. notes: 1. input voltages may exceed the supply voltages provided that input current is limited to 100 m a. current above this value may result in invalid display readings but will not destroy the device if limited to 1ma. 2. dissipation ratings assume device is mounted with all leads soldered to printed circuit board. tc820 3-3/4 digit a/d converter with frequency and logic probe
3-152 telcom semiconductor, inc. electrical characteristics (cont.) symbol parameter test conditions min typ max units buzzer frequency f osc = 40khz 5 khz counter timebase period f osc = 40khz 1 second low battery flag voltage v dd to v ss 6.7 7 7.3 v v il input low voltage dgnd + 1.5 v v ih input high voltage v dd C 1.5 v v ol output low voltage, i l = 50 m a dgnd + 0.4 v ur, or outputs v ol output high voltage, i l = 50 m av dd C 1.5 v ur, or outputs control pin v in = v dd 5 m a pull-down current pin description pin no. pin no. (40-pin (44-pin flat package) package) symbol description 1 40 l-e4 lcd segment driver for l ("logic low"), polarity, and "e" segment of most significant digit (msd). 2 41 agd4 lcd segment drive for "a," "g," and "d" segments of msd. 3 42 bc4p3 lcd segment drive for "b" and "c" segments of msd and decimal point 3. 4 43 hfe3 lcd segment drive for h ("logic high"), and "f" and "e" segments of third lsd. 5 44 agd3 lcd segment drive for "a," "g," and "d" segments of third lsd. 6 1 bc3p2 lcd segment drive for "b" and "c" segments of third lsd and decimal point 2. 7 2 ofe2 lcd segment drive for "overrange," and "f" and "e" segments of second lsd. 8 3 agd2 lcd segment drive for "a," "g," and "d" segments of second lsd. 9 4 bc2p1 lcd segment drive for "b " and "c" segments of second lsd and decimal point 1. 10 5 pkfe1 lcd segment drive for "hold peak reading," and "f" and "e" segments of lsd. 11 6 agd1 lcd segment drive for "a," "g," and "d" segments of lsd. 12 7 bc1bt lcd segment drive for "b" and "c" segments of lsd and "low battery." 13 8 bp3 lcd backplane #3. 14 9 bp2 lcd backplane #2. 15 10 bp1 lcd backplane #1. 11v disp sets peak lcd drive signal: v peak = (v dd ) Cv disp . v disp may also be used to compensate for temperature variation of lcd crystal threshold voltage. 16 12 dgnd internal logic digital ground, the logic "0" level. nominally 4.7v below v dd . 17 13 annunc square-wave output at the backplane frequency, synchronized to bp1. annunc can be used to control display annunciators. connecting an lcd segment to annunc turns it on; connecting it to its backplane turns it off. 18 14 logic logic mode control input. when connected to v dd , the converter is in logic mode. the lcd displays "ol" and the decimal point inputs control the high and low annunciators. when the "low" annunciator is on, the buzzer will also be on. when unconnected or connected to dgnd, the tc820 is in the voltage/frequency measurement mode. this pin has a 5 m a internal pull-down to dgnd. 19 15 range/ dual-purpose input. in range mode, when connected to v dd , the integration time freq will be 200 counts instead of 2000 counts and the lcd will display the analog input divided by 10. (see text for limitation with tc820.) in frequency mode, this pin is the frequency input. a digital signal applied to this pin will be measured with a 1-second time base. there is an internal 5 m a pull-down to dgnd. 3-3/4 a/d converter with frequency counter and logic probe tc820
3-153 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 pin description pin no. pin no. (40-pin (44-pin flat package) package) symbol description 20 16 dp0/lo dual-purpose input. decimal point select input for voltage measurements. in logic mode, connecting this pin to v dd will turn on the "low" lcd segment. there is an internal 5 m a pull-down to dgnd in volts mode only. decimal point logic: dp1 dp0 decimal point selected 0 0 none 0 1 dp1 1 0 dp2 1 1 dp3 21 17 dp1/hi dual-purpose input. decimal point select input for voltage measurements. in logic mode, connecting this pin to v dd will turn on the "high" lcd segment. there is an internal 5 m a pull-down to dgnd in volts mode only. 22 18 buzout buzzer output. audio frequency, 5khz, output which drives a piezoelectric buzzer. 23 19 buzin buzzer control input. connecting buzin to v dd turns the buzzer on. buzin is logically ored (internally) with the "logic level low" input. there is an internal 5 m a pull-down to dgnd. 24 20 freq/ voltage or frequency measurement select input. when unconnected, or connected volts to dgnd, the a/d converter function is active. when connected to v dd , the frequency counter function is active. this pin has an internal 5 m a pull-down to dgnd. 25 21 pkhold peak hold input. when connected to v dd , the converter will only update the display if a new conversion value is greater than the preceding value. thus, the peak reading will be stored and held indefinitely. when unconnected, or connected to dgnd, the converter will operate normally. this pin has an internal 5 m a pull-down to dgnd. 22 ur underrange output. this output will be high when the digital reading is 380 counts or less. 23 or overrange output. this output will be high when the analog signal input is greater than full scale. the lcd will display "ol" when the input is overranged. 26 24 v ss negative supply connection. connect to negative terminal of 9v battery. 27 25 com analog circuit ground reference point. nominally 3.3v below v dd . 28 26 c + ref positive connection for reference capacitor. 29 27 c C ref negative connection for reference capacitor. 30 28 v + ref high differential reference input connection. 31 29 v C ref low differential reference input connection. 32 30 v C in low analog input signal connection. 33 31 v + in high analog input signal connection. 34 32 v buff buffer output. connect to integration resistor. 35 33 c az auto-zero capacitor connection. 36 34 v int integrator output. connect to integration capacitor. 35 eoc/ bidirectional pin. pulses low (i.e., from v dd to dgnd) at the end of each hold conversion. if connected to v dd , conversions will continue, but the display is not updated. 37 36 osc1 crystal oscillator (input) connection. 38 37 osc2 crystal oscillator (output) connection. 39 38 osc3 rc oscillator connection. 40 39 v dd positive power supply connection, typically 9v. tc820 3-3/4 a/d converter with frequency counter and logic probe
3-154 telcom semiconductor, inc. 3-3/4 a/d converter with frequency counter and logic probe tc820 pin configurations tc820cpl 1 2 3 4 osc1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 osc2 osc3 c ref com v pk hold freq/volts buz in buz out dp1/hi dp0/lo 27 28 29 30 31 32 33 7 4 3 2 1 c 12 13 14 15 17 18 44 43 42 41 39 38 40 agd3 16 37 36 35 int 34 v 19 20 21 22 26 8 25 9 24 10 23 11 5 6 bc3p2 dgnd 33 34 35 36 37 38 39 13 10 9 8 7 c 18 19 20 21 23 24 ur 6543 144 2 agd3 agd4 osc3 22 43 osc2 42 osc1 41 eoc/hold 40 v 25 26 27 28 32 14 31 15 30 16 29 17 v hfe3 bc4p3 11 12 disp TC820CLW v buff tc820ckw ss + c ref v ref + v ref v in v in + v buff c az v int v dd range/freq logic annunc dgnd bp1 bp2 bp3 segments bc1bt segments agd1 segments pkfe1 segments bcp1 segments agd2 segments ofe2 segments bc3p2 segments agd3 segments hfe3 segments bc4p3 segments agd4 segments l-e4 l-e4 v dd int az v + in v in v ref v + ref c ref c + ref com v ss or pk hold freq/volts buz in buz out dp1/hi dp0/lo range/freq logic annunc dgnd bp1 bp2 bp3 bp1bt bc3p2 ofe2 agd2 bc2p1 pkfe1 agd1 l?4 az ur pk hold agd2 ofe2 v disp bcp2p1 pkfe1 bp2 osc1 v ss or com c ref + bc4p3 osc3 osc2 eoc/hold annunc freq/volts buz in buz out dp1/hi dp0/lo range/freq logic bp1 bp3 bp1bt agd1 v buff v + in v in v ref v + ref c ref hfe3 agd4 v dd
3-155 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc820 3-3/4 a/d converter with frequency counter and logic probe functional block diagram range/freq input triplex drivers display latch comparator a > b a/d counter (3999 counts) logic low logic dp0/lo dp1/hi range/ freq freq/ volts buzzer driver buz in logic low osc3 osc2 osc1 frequency counter input a/d counter select range sel b a low batt low batt detect a/d control deint underrange overrange range eoc dgnd ur or eoc/ hold peak hold annunc seg0 ???bp3 v disp 15 to lcd v int c az common v dd v ss v + ref v ref tc820 v + in v in c + ref c ref v buff 2 8
3-156 telcom semiconductor, inc. 3-3/4 a/d converter with frequency counter and logic probe tc820 general theory of operation dual-slope conversion principles the tc820 analog-to-digital converter operates on the principle of dual-slope integration. an understanding of the dual-slope conversion technique will aid the user in follow- ing the detailed tc820 theory of operation following this section. a conventional dual-slope converter measurement cycle has two distinct phases: (1) input signal integration (2) reference voltage integration (deintegration) referring to figure 2, the unknown input signal to be converted is integrated from zero for a fixed time period (t int ), measured by counting clock pulses. a constant reference voltage of the opposite polarity is then integrated until the integrator output voltage returns to zero. the reference integration (deintegration) time (t deint ) is then directly proportional to the unknown input voltage (v in ). in a simple dual-slope converter, a complete conver- sion requires the integrator output to "ramp-up" from zero and "ramp-down" back to zero. a simple mathematical equation relates the input signal, reference voltage, and integration time: 9v l-e4 agd4 bc4p3 bc3p2 ofe2 agd2 bc2p1 pk fe1 agd1 bc1bt bp3 bp2 bp1 hfe3 agd3 10 11 12 13 14 15 17 9 8 7 6 5 4 3 2 1 logic high logic low overrange pkhold low batt freq/ volts logic dp0/lo dp1/hi dgnd nc annunc com buz out buz in pk hold 30 31 27 40 26 22 23 25 osc1 osc2 osc3 v buff c az v int v dd v ss v + ref v ref tc820 c + ref c ref 24 18 33 32 16 19 20 21 v + in v in 37 38 39 34 35 36 28 29 40khz 470 k w nc 100 k w 0.47 f 0.2 f 0.1 f 22m w note: pin numbers are for 40-pin package. piezo buzzer dgnd dgnd v dd v dd v dd 1 f + v dd 22k w 2k w v ref = 200mv change range to switch s1a no dp s2 dp3 dp2 dp1 dgnd s1e s1d logic freq gnd v in v dd s1c s1b s1a to switch s2 100k w 0.01 f v dd v dd com range/freq + + ref voltage analog input signal + display switch driver control logic integrator output clock counter polarity control phase control v in v in v full scale 1.2 v full scale variable reference integrate time fixed signal integrate time integrator c comparator r = = figure 2. basic dual-slope converter figure 1. typical operating circuit
3-157 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 where: v ref = reference voltage t int = integration time t deint = deintegration time for a constant t int : v in = v ref 3 0 t deint t int accuracy in a dual-slope converter is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. an inherent benefit of the dual-slope technique is noise immunity. noise spikes are integrated or averaged to zero during the integration periods, making integrating adcs immune to the large conversion errors that plague successive approximation converters in high-noise environments. interfering signals, with frequency components at multiples of the averaging (integrating) period, will be attenuated (figure 3). integrating adcs commonly operate with the signal integration period set to a multiple of the 50/60hz power line period. figure 3. normal-mode rejection of dual-slope converter 30 20 10 0 0.1/t 1/t 10/t input frequency normal mode rejection (db) t = measurement period analog section in addition to the basic integrate and deintegrate dual- slope phases discussed above, the tc820 design incorpo- rates a "zero integrator output" phase and an "auto-zero" phase. these additional phases ensure that the integrator starts at 0v (even after a severe overrange conversion), and that all offset voltage errors (buffer amplifier, integrator and comparator) are removed from the conversion. a true digital zero reading is assured without any external adjustments. a complete conversion consists of four distinct phases: (1) zero integrator output (2) auto-zero (3) signal integrate (4) reference deintegrate zero integrator output phase this phase guarantees that the integrator output is at 0v before the system zero phase is entered, ensuring that the true system offset voltages will be compensated for even after an overrange conversion. the duration of this phase is 500 counts plus the unused deintegrate counts. auto-zero phase during the auto-zero phase, the differential input signal is disconnected from the measurement circuit by opening internal analog switches, and the internal nodes are shorted to analog common (0v ref ) to establish a zero input condi- tion. additional analog switches close a feedback loop around the integrator and comparator to permit comparator offset voltage error compensation. a voltage established on c az then compensates for internal device offset voltages during the measurement cycle. the auto-zero phase re- sidual is typically 10 m v to 15 m v. the auto-zero duration is 1500 counts. signal integration phase upon completion of the auto-zero phase, the auto-zero loop is opened and the internal differential inputs connect to v in + and v in C . the differential input signal is then integrated for a fixed time period, which is 2000 counts (4000 clock periods). the externally-set clock frequency is divided by two before clocking the internal counters. the integration time period is: t int = the differential input voltage must be within the device's common-mode range when the converter and measured system share the same power supply common (ground). if the converter and measured system do not share the same power supply common, as in battery-powered applications, v in C should be tied to analog common. polarity is determined at the end of signal integration phase. the sign bit is a "true polarity" indication in that signals less than 1 lsb are correctly determined. this allows precision null detection that is limited only by device noise and auto-zero residual offsets. 1 r int c int t int v in (t) dt = v ref t deint r int c int 4000 f osc tc820 3-3/4 a/d converter with frequency counter and logic probe
3-158 telcom semiconductor, inc. 3-3/4 a/d converter with frequency counter and logic probe tc820 peak reading hold the tc820 provides the capability of holding the highest (or peak) reading. connecting the pk hold input to v dd enables the peak hold feature. at the end of each conversion the contents of the tc820 counter is compared to the contents of the display register. if the new reading is higher than the reading being displayed, the higher reading is transferred to the display register. a "higher" reading is defined as the reading with the higher absolute value. the peak reading is held in the display register so the reading will not "droop" or slowly decay with time. the held reading will be retained until a higher reading occurs, the pk hold input is disconnected from v dd , or power is removed. the peak signal to be measured must be present during the tc820 signal integrate period. the tc820 does not perform transient peak detection of the analog input signal. however, in many cases, such as measuring temperature or electric motor starting current, the tc820 "acquisition time" will not be a limitation. if true peak detection is required, a simple circuit will suffice. see the applications section for details. the peak reading function is also available when the tc820 is in the frequency counter mode. the counter auto- ranging feature is disabled when peak reading hold is selected. 10:1 range change the analog input full-scale range can be changed with the range/freq input. normally, range/freq is held low by an internal pulldown. connecting this pin to v s + will increase the full-scale voltage by a factor of 10. no external component changes are required. the range/freq input operates by changing the integrate period. when range/freq is connected to v dd , the signal integration phase of the conversion is reduced by a factor of 10 (i.e., from 2000 counts to 200 counts). for the tc820, the 10:1 range change will result in 4v full scale. this full-scale range will exceed the common- mode range of the input buffer when operating from a 9v battery. if range changing is required for the tc820, a higher supply voltage can be provided or the input voltage can be divided by 2 externally. frequency counter in addition to serving as an analog-to-digital converter, the tc820 internal counter can also function as a frequency counter (figure 4). in the counter mode, pulses at the range/freq input will be counted and displayed. the frequency counter derives its time base from the clock oscillator. the counter time base is: t count = f osc 40,000 reference integrate (deintegrate) phase the reference capacitor, which was charged during the auto-zero phase, is connected to the input of the integrating amplifier. the internal sign logic ensures the polarity of the reference voltage is always connected in the phase opposite to that of the input voltage. this causes the integrator to ramp back to zero at a constant rate determined by the reference potential. the amount of time required (t deint ) for the integrating amplifier to reach zero is directly proportional to the ampli- tude of the voltage that was put on the integrating capacitor (v int ) during the integration phase: t deint = the digital reading displayed by the tc820 is: digital count = 2000 system timing the oscillator frequency is divided by 2 prior to clocking the internal decade counters. the four-phase measurement cycle takes a total of 8000 (4000) counts or 16000 clock pulses. the 8000 count phase is independent of input signal magnitude or polarity. each phase of the measurement cycle has the following length: conversion phase counts 1) auto-zero: 1500 2) signal integrate: 1,2 2000 3) reference integrate: 1 to 4001 4) integrator output zero: 499 to 4499 notes: 1. this time period is fixed. the integration period for the tc820 is: t int (tc820) = = 2000 counts where f osc is the clock oscillator frequency. 2. times shown are the range/freq at logic low (normal operation). when range/freq is logic high, signal integrate times are 200 counts. see "10:1 range change" section. r int c int v int v ref v + in C v C in v ref input overrange when the analog input is greater than full scale, the lcd will display "ol" and the "overrange" lcd annunciator will be on. 4000 f osc
3-159 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 if the logic probe is active while freq/volts is high (counter mode), the frequency counter will continue to operate. the display will read "ol" but the decimal points will be visible. if the logic probe input is also connected to the range/freq input, bringing the logic input low will immediately display the frequency at the logic probe input. analog pin functional description differential signal inputs (v + in ), (v C in ) the tc820 is designed with true differential inputs, and accepts input signals within the input stage common-mode voltage (v cm ) range. the typical range is v dd C1v to v ss +1.5v. common-mode voltages are removed from the sys- tem when the tc820 operates from a battery or floating power source (isolated from measured system) and v ss is connected to analog common. (see figure 8.) tc820 3-3/4 a/d converter with frequency counter and logic probe thus, the counter will operate with a 1-second time base when a 40 khz oscillator is used. the frequency counter accuracy is determined by the oscillator accuracy. for accurate frequency measurements, a crystal oscillator is recommended. the frequency counter will automatically select the proper range. auto-range operation extends over four decades, from 3.999 khz to 3.999 mhz. decimal points are set automatically in the frequency mode (figure 5). the logic switching levels of the range/freq input are cmos levels. for best counter operation, an external buffer is recommended. see the applications section for details. logic probe the tc820 can also function as a simple logic probe (figure 6). this mode is selected when the logic input is high. two dual-purpose pins, which normally control the decimal points, are used as logic inputs. connecting either input to a logic high level will turn on the corresponding lcd annunciator. when the "low" annunciator is on the buzzer will be on. as with the frequency counter input, external level shifters/buffers are recommended for the logic probe inputs. when the logic probe function is selected while freq/ volts is low (a/d mode), the adc will remain in the auto- zero mode. the lcd will read "ol" and all decimal points will be off (figure 7). data latch, peak hold register, lcd decoder/drivers overrange detect underrange detect auto-range control programmable divider ( 1, 10, 100, 1000) clock oscillator to decimal point drivers frequency input range/ freq 20,000 from integrator of a/d converter comparator lcd 3-3/4 digit counter enable count overflow a/d converter frequency counter a/d converter/frequency counter select tc820 2 freq/ volts figure 4. tc820 counter operation
3-160 telcom semiconductor, inc. 3-3/4 a/d converter with frequency counter and logic probe tc820 in systems where common-mode voltages exist, the 86db common-mode rejection ratio minimizes error. com- mon-mode voltages do, however, affect the integrator out- put level. a worst-case condition exists if a large, positive v cm exists in conjunction with a full-scale, negative differen- tial signal. the negative signal drives the integrator output positive along with v cm (figure 9). for such applications, the integrator output swing can be reduced below the recom- mended 2v full-scale swing. the integrator output will swing within 0.3v of v dd or v dd without increased linearity error. reference (v dd , v ss ) the tc820 reference, like the analog signal input, has true differential inputs. in addition, the reference voltage can be generated anywhere within the power supply voltage of the converter. the differential reference inputs permit ratiometric measurements and simplify interfacing with sen- sors, such as load cells and temperature sensors. dp3 dp2 dp1 0hz ?3999hz 4khz ?39.99khz 40khz ?399.9khz 400khz 3 dp3 dp2 dp1 none decimal point f in figure 5. tc820 auto-range decimal point selection vs frequency counter input high low lcd drivers disable a/d converter to buzzer dp0/lo dp1/hi logic cmos logic levels external logic level detection and pulse stretching v dd tc820 logic probe input nc lcd figure 6. logic probe simplified schematic
3-161 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc820 3-3/4 a/d converter with frequency counter and logic probe to prevent roll-over-type errors from being induced by large common-mode voltages, c ref should be large com- pared to stray node capacitance. a 0.1 m f capacitor is typical. the tc820 offers a significantly improved analog common temperature coefficient, providing a very stable voltage suitable for use as a voltage reference. the temperature coefficient of analog common is typically 35ppm/ c. figure 7. lcd during logic probe operation high low * ** "high" annunciator will be on when dp1/hi = logic high "low" annunciator and buzzer will be on when dp0/lo = logic high ** * analog common the analog common pin is set at a voltage potential approximately 3.3v below v dd . this potential is guaranteed to be between 3.15v and 3.45v below v dd . analog common is tied internally to an n-channel fet capable of sinking 3ma. this fet will hold the common line at 3.3v below v dd should an external load attempt to pull the common line toward v dd . analog common source current is limited to 12 m a, and is therefore easily pulled to a more negative voltage (i.e., below v dd C 3.3v). the tc820 connects the internal v + in and v C in inputs to analog common during the auto-zero cycle. during the reference integrate phase, v C in is connected to analog common. if v C in is not externally connected to analog common, a common-mode voltage exists. this is rejected by the converter's 86db common-mode rejection ratio. in battery- powered applications, analog common and v C in are usually connected, removing common-mode voltage concerns. in systems where v C in is connected to the power supply ground or to a given voltage, analog common should be connected to v C in . the analog common pin serves to set the analog section reference or common point. the tc820 is specifically designed to operate from a battery or in any measurement tc820 gnd gnd v + v v + v measured system power source 9v v in v dd v ss v + ref v ref + v in v buf c az bp1 int v bp3 bp2 osc1 osc2 osc3 nc segment drive lcd analog common + figure 8. common-mode voltage removed in battery operation with v C in = analog common
3-162 telcom semiconductor, inc. 3-3/4 a/d converter with frequency counter and logic probe tc820 table i. tc820 control input truth table logic input freq/ range/ tc820 volts freq logic function x x 1 logic probe 0 0 0 a/d converter, v full scale = 2 3 v ref 0 1 0 a/d converter, v full scale = 20 3 v ref 1 frequency 0 frequency counter counter input notes: 1. logic "0" = dgnd 2. logic "1" = v dd figure 9. common-mode voltage reduces available integrator swing (v com t v in ) + + r i c i v i v in integrator input buffer + t i = integration time = c i = integration capacitor r i = integration resistor 4000 f v cm osc where: v i = [ [ v cm v in t i r i c i freq/volts this input determines whether the tc820 is in the analog-to-digital conversion mode or in the frequency counter mode. when freq/volts is connected to v dd , the tc820 will measure frequency at the range/freq input. when unconnected, or connected to dgnd, the tc820 will oper- ate as an analog-to-digital converter. this input has an internal 5 m a pull-down to dgnd. logic the logic input is used to activate the logic probe function. when connected to v dd , the tc820 will enter the logic probe mode. the lcd will show "ol" and all decimal points will be off. the decimal point inputs directly control "high" and "low" display annunciators. when logic is unconnected, or connected to dgnd, the tc820 will per- form analog-to-digital or frequency measurements as se- lected by the freq/volts input. the logic input has an internal 5 m a pull-down to dgnd. system where input signals are not referenced (float) with respect to the tc820 power source. the analog common potential of v dd C 3.3v gives a 7v end-of-battery-life voltage. the analog common potential has a voltage coefficient of 0.001%/%. with a sufficiently high total supply voltage (v dd C v ss > 7v), analog common is a very stable potential with excellent temperature stability (typically 35ppm/ c). this potential can be used to generate the tc820 reference voltage. an external voltage reference will be unnecessary in most cases, because of the 35ppm/ c temperature coefficient. see the applications section for details. function control input pin functional description the tc820 operating modes are selected with the function control inputs. the control input truth table is shown in table i. the high logic threshold is 3 v dd - 1.5v and the low logic level is dgnd +1.5v. range/freq the function of this dual-purpose pin is determined by the freq/volts input. when freq/volts is connected to v dd , range/freq is the input for the frequency counter function. pulses at this input are counted with a time base equal to f osc /40,000. since this input has cmos input levels (v dd - 1.5v and dgnd +1.5v), an external buffer is recom- mended. when the tc820 analog-to-digital converter function is selected, connecting range/freq to v dd will divide the integration time by 10. therefore, the range/freq input can be used to perform a 10:1 range change without changing external components. dp0/lo, dp1/hi the function of these dual-purpose pins is determined by the logic input. when the tc820 is in the analog-to- digital converter mode, these inputs control the lcd decimal points. the decimal point truth table is shown in table ii. these inputs have internal 5 m a pull-downs to dgnd when the voltage/frequency measurement mode is active. table ii. tc820 decimal point truth table decimal point inputs dp1 dp0 lcd 0 0 3999 0 1 399.9 1 0 39.99 1 1 3.999
3-163 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc820 3-3/4 a/d converter with frequency counter and logic probe additional features the tc820 is available in 40-pin and 44-pin packages. several additional features are available in the 44-pin pack- age. eoc/hold eoc/hold is a dual-purpose, bidirectional pin. as an output, this pin goes low for 10 clock cycles at the end of each conversion. this pulse latches the conversion data into the display driver section of the tc820. eoc/hold can be used to hold (or "freeze") the dis- play. connecting this pin to v dd inhibits the display update process. conversions will continue, but the display will not change. eoc/hold will hold the display reading for either analog-to-digital or frequency measurements. the input/output structure of the eoc/hold pin is shown in figure 10. the output drive current is only a few microamps, so eoc/hold can easily be overdriven by an open-collector logic gate, as well as a fet, bipolar transis- tor, or mechanical switch. when used as an output, eoc/ hold will have a slow rise and fall time due to the limited output current drive. a cmos schmitt trigger buffer is recommended. connecting the logic input to v dd places the tc820 in the logic probe mode. in this mode, the dp0/lo and dp1/ hi inputs control the lcd "low" and "high" annunciators directly. when dp1/hi is connected to v dd , the "high" annunciator will turn on. when dp0/lo is connected to v dd , the "low" annunciator and the buzzer will turn on. the internal pull-downs on these pins are disabled when the logic probe function is selected. these inputs have cmos logic switching thresholds. for optimum performance as a logic probe, external level shifters are recommended. see the applications section for details. buz in this input controls the tc820 on-chip buzzer driver. connecting buz in to v dd will turn the buzzer on. there is an external pull-down to dgnd. buz in can be used with external circuitry to provide additional functions, such as a fast, audible continuity indication. figure 10. eoc/hold pin schematic w 4 500 k ? eoc/hold display update eoc tc820 overrange (or), underrange (ur) the or output will be high when the analog input signal is greater than full scale (3999 counts). the ur output will be high when the display reading is 380 counts or less. the or and ur outputs can be used to provide an auto- ranging meter function. by logically anding these outputs with the inverted eoc/hold output, a single pulse will be generated each time an underranged or overranged conver- sion occurs (figure 11). v disp the v disp input sets the peak-to-peak lcd drive volt- age. in the 40-pin package, v disp is connected internally to dgnd, providing a typical lcd drive voltage of 5v p-p . the 44-pin package includes a separate v disp input for applica- tions requiring a variable or temperature-compensated lcd drive voltage. see the applications information for sug- gested circuits. eoc/hold tc820 ur or 74hc132 * * * * figure 11. generating underrange and overrange pulses
3-164 telcom semiconductor, inc. 3-3/4 a/d converter with frequency counter and logic probe tc820 digital ground (dgnd) digital ground is generated from an internal zener diode (figure 14). the voltage between v dd and dgnd is the internal supply voltage for the digital section of the tc820. dgnd will sink a minimum of 3ma. dgnd establishes the low logic level reference for the tc820 mode select inputs, and for the frequency and logic probe inputs. the dgnd pin can be used as the negative supply for external logic gates, such as the logic probe buffers. to ensure correct counter operation at high fre- quency, connect a 1 m f capacitor from dgnd to v dd . dgnd also provides the drive voltage for the lcd. the tc820 40-pin package internally connects the lcd v disp pin to dgnd, and provides an lcd drive voltage of about 5v p-p . in the 44-pin package, connecting the v disp pin to dgnd will provide a 5v lcd drive voltage. digital input logic levels logic levels for the tc820 digital inputs are referenced to v dd and dgnd. the high-level threshold is v dd C 1.5v and the low logic level is dgnd +1.5v. in most cases, digital inputs will be connected directly to v dd with a mechanical switch. cmos gates can also be used to control the logic inputs, as shown in the logic probe inputs section. figure 13. powering the tc820 from a low-voltage battery v disp the v disp input sets the peak-to-peak lcd drive volt- age. in the 40-pin package, v disp is connected internally to dgnd, providing a typical lcd drive voltage of 5 v p-p . the 44-pin package includes a separate v disp input for applica- tions requiring a variable or temperature-compensated lcd drive voltage. see the applications information for sug- gested circuits. applications information power supplies the tc820 is designed to operate from a single power supply such as a 9v battery (figure 12). the converter will operate over a range of 7v to 15v. for battery operation, analog common (com) provides a common-mode bias voltage (see analog common discussion in the theory of operation section). however, measurements cannot be referenced to battery ground. to do so will exceed the negative common-mode voltage limit. a battery with voltage between 3.5v and 7v can be used to power the tc820, when used with a voltage doubler, as shown in figure 13. the voltage doubler uses the tc7660 and two external capacitors. with this configuration mea- surements can be referenced either to analog common or to battery ground. figure 12. powering the tc820 from a single 9v battery tc820 v in v ref v dd v + ref com v + in v in v ss + 9v + v dd v ss v + ref v ref tc820 3.5v to 6v tc7660 tc04 v in v in + + v in 10 f 3 4 2 8 5 10 f + + + com
3-165 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 tc820 3-3/4 a/d converter with frequency counter and logic probe figure 15. suggested crystal oscillator circuit 5pf 37 38 39 110k w 10pf 75pf tc820 figure 14. dgnd and com outputs + 12 a p tc820 logic section 5v 3.2v n n v dd v ss com dgnd figure 16. r-c oscillator circuit typical values are r = 10k w and c = 68pf. the resistor value should be 3 100k w . for accurate frequency measure- ment, an r-c oscillator frequency of 40khz is required. system timing all system timing is derived from the clock oscillator. the clock oscillator is divided by 2 prior to clocking the a/d counters. the clock is also divided by 8 to drive the buzzer, by 240 to generate the lcd backplane frequency, and by 40,000 for the frequency counter time base. a simplified diagram of the system clock is shown in figure 17. component value selection auto zero capacitor c az the value of the auto-zero capacitor (c az ) has some influence on system noise. a 0.47 m f capacitor is recom- mended; a low dielectric absorption capacitor (mylar) is required. reference voltage capacitor c ref the reference voltage capacitor used to ramp the inte- grator output voltage back to zero during the reference integrate cycle is stored on c ref . a 0.1 m f capacitor is typical. a good quality, low leakage capacitor (such as mylar) should be used. integrating capacitor c int c int should be selected to maximize integrator output voltage swing without causing output saturation. analog common will normally supply the differential voltage reference. for this case, a 2v integrator output swing is optimum when the analog input is near full scale. for 2.5 readings/second (f osc = 40khz) and v fs = 400mv, a 0.22 m f value is suggested. if a different oscillator frequency is used, c int must be changed in inverse proportion to maintain the 0.3 rc clock oscillator the tc820 oscillator can be controlled with either a crystal or with an inexpensive resistor-capacitor combina- tion. the crystal circuit, shown in figure 15, is recommended when high accuracy is required in the frequency counter mode. the 40khz crystal is a standard frequency for ultra- sonic alarms, and will provide a 1-second time base for the counter or 2.5 analog-to-digital conversions per second. consult the crystal manufacturer for detailed applications information. where low cost is important, the r-c circuit of figure 16 can be used. the frequency of this circuit will be approxi- mately: f osc = tc820 40khz 38 39 5 pf 10pf 22 m w 470k w 37
3-166 telcom semiconductor, inc. 3-3/4 a/d converter with frequency counter and logic probe tc820 figure 17. system clock generation nominal 2v integrator swing. an exact expression for c int is: c int = where: f osc = clock frequency v fs = full-scale input voltage r int = integrating resistor v int = desired full-scale integrator output swing c int must have low dielectric absorption to minimize roll-over error. a polypropylene capacitor is recommended. integrating resistor r int the input buffer amplifier and integrator are designed with class a output stages. the integrator and buffer can supply 40 m a drive currents with negligible linearity errors. r int is chosen to remain in the output stage linear drive region but not so large that printed circuit board leakage currents induce errors. for a 400mv full scale, r int should be about 100k w . reference voltage selection a full-scale reading (4000 counts for tc820) requires the input signal be twice the reference voltage. table iii. reference voltage selection full-scale input voltage (v fs ) (note 1) v ref resolution 200mv note 2 C 400mv 200mv 10 m v 1v 500mv 250 m v 2v 1v 500 m v (notes 3, 4) notes: 1. tc820 in a/d converter mode, range/freq = logic low. 2. not recommended. 3. v fs > 2v may exceed the input common mode range. see "10:1 range change" section. 4. full-scale voltage values are not limited to the values shown. for example, tc820 v fs can be any value from 400mv to 2v. in some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. assume, for example, that a pressure trans- ducer output is 800mv for 4000 lb/in 2 . rather than dividing the input voltage by two, the reference voltage should be set to 400mv. this permits the transducer input to be used directly. the internal voltage reference potential available at analog common will normally be used to supply the converter's reference voltage. this potential is stable when- ever the supply potential is greater than approximately 7v. the low-battery detection circuit and analog common oper- ate from the same internal reference. this ensures that the low-battery annunciator will turn on at the time the internal reference begins to lose regulation. the tc820 can also operate with an external reference. figure 18 shows internal and external reference applica- tions. ratiometric resistance measurements the tc820 true differential input and differential refer- ence make ratiometric readings possible. in ratiometric operation, an unknown resistance is measured with respect to a known standard resistance. no accurately defined reference voltage is needed. the unknown resistance is put in series with a known standard and a current is passed through the pair (fig- ure 19). the voltage developed across the unknown is applied to the input and voltages across the known resistor a/d counter tc820 40,000 counter time base 240 lcd backplane driver 8 buzzer 2 osc1 osc2 osc3 xtal oscillator components r/c oscillator components 4000 v fs v int r int f osc
3-167 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 v dd tc820 logic probe input +9v 74hc14 logic dp1/hi dp0/lo dgnd * * * tc820 3-3/4 a/d converter with frequency counter and logic probe figure 18. reference voltage connections figure 20. frequency counter external buffer logic probe inputs the dp0/lo and dp1/hi inputs provide the logic probe inputs when the logic input is high. driving either dp0/lo or dp1/hi to a logic high will turn on the appropriate lcd annunciator. when dp0/lo is high, the buzzer will be on. to provide a "single input" logic probe function, external buffers should be used. a simple circuit is shown in figure 21. this circuit will turn the appropriate annunciator on for high and low level inputs. if carefully controlled logic thresholds are required, a window comparator can be used. figure 22 shows a typical circuit. this circuit will turn on the high or low annunciators when the logic thresholds are exceeded, but the resistors connected from dp0/lo and dp1/hi to dgnd will turn both annunciators off when the logic probe is unconnected. the tc820 logic inputs are not latched internally, so pulses of short duration will usually be difficult or impossible to see. to display short pulses properly, the input pulse should be "stretched." the circuit of figure 22 shows cap- figure 21. simple external logic probe buffer applied to the reference input. if the unknown equals the standard, the input voltage will equal the reference voltage and the display will read 2000. the displayed reading can be determined from the following expression: displayed reading = 3 2000 the display will overrange for values of r unknown 3 2 3 r standard . buffering the freq input when the freq/volts input is high and the logic input is low, the tc820 will count pulses at the range/ freq input. the time base will be f osc /40,000, or 1 second with a 40khz clock. the signal to be measured should swing from v dd to dgnd. the range/freq input has cmos input levels without hysteresis. for best results, especially with low-frequency sine-wave inputs, an external buffer with hysteresis should be added. a typical circuit is shown in figure 20. figure 19. low parts count ratiometric resistance measurement 9v tc820 tc820 + 22k w v dd v dd v ss v + ref v ref analog common set v = 1/2 v ref full scale (a) internal reference (b) external reference v + ref v ref common v + tc04a 1.2v ref 2k w v ref 2k w tc820 + dgnd frequency input gnd dgnd 74hc14 range/freq freq/volts v dd 1 f +9v r unknown r standard tc820 r standard r unknown analog common v dd v + ref v ref v + in v in lcd
3-168 telcom semiconductor, inc. 3-3/4 a/d converter with frequency counter and logic probe tc820 figure 22. window comparator logic probe acitors added across the input pull-down resistors to stretch the input pulse and permit viewing short-duration input pulses. external peak detection the tc820 will hold the highest a/d conversion or frequency reading indefinitely when the pk hold input is connected to v dd . however, the analog peak input must be present during the a/d converter's signal integrate period. for slowly changing signals, such as temperature, the peak reading will be properly converted and held. if rapidly changing analog signals must be held, an external peak detector should be added. an inexpensive circuit can be made from an op amp and a few discrete components, as shown in figure 23. the droop rate of the external peak detector should be adjusted so that the held voltage will not decay below the desired accuracy level during the converter's 400msec conversion time. liquid crystal display (lcd) the tc820 drives a triplex (multiplexed 3:1) lcd with three backplanes. the lcd can include decimal points, polarity sign, and annunciators for overrange, peak hold, high and low logic levels, and low battery. table iv shows the assignment of the display segments to the backplanes and segment drive lines. the backplane drive frequency is obtained by dividing the oscillator frequency by 240. backplane waveforms are shown in figure 24. these appear on outputs bp1, bp2, and bp3. they remain the same regardless of the segments being driven. other display output lines have waveforms that vary + v dd tc820 r1 dp1/hi logic dp0/lo dgnd 1n4148 1n4148 +9v v l r2 r3 1m w 1m w logic probe input note: select r1, r2, r3 for desired logic thresholds. + v h depending on the displays values. figure 25 shows a set of waveforms for the a, g, d outputs of one digit for several combinations of "on" segments. figure 23. external peak detector v dd tc820 + v ss v + in pk hold 0v 0.01 f offset null 1n4148 +9v 10k w v in tl061 table iv. lcd backplane and segment assignments 44-pin lcd 40-pin dip flat pkg display pin no. pin no. pin no. bp1 bp2 bp3 1 40 3 low "" e4 2 41 4 a4 g4 d4 3 42 5 b4 c4 dp3 4 43 6 high f3 e3 5 44 7 a3 g3 d3 6 1 8 b3 c3 dp2 7 2 9 over f2 e2 8 3 10 a2 g2 d2 9 4 11 b2 c2 dp1 10 5 12 peak f1 e1 11 6 13 a1 g1 d1 12 7 14 b1 c1 batt 13 8 2,16* bp3 14 9 1 bp2 15 10 15 bp1 *connect both pins 2 and 16 of lcd to tc820 bp3 output.
3-169 telcom semiconductor, inc. 7 6 5 4 3 1 2 8 bp1 bp2 bp3 tc820 3-3/4 a/d converter with frequency counter and logic probe v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp segment line all off a segment on d, g off a, g on d off all on figure 24. backplane waveforms lcd source although most users will design their own custom lcd, a standard display for the tc820 (figure 26), part no. st- 1355-m1, is available from: crystaloid (usa) crystaloid (europe) crystaloid electronics rep france p.o. box 628 102, rue des nouvelles 5282 hudson dr. f92150 suresnes hudson, oh 44238 france phone: (216) 655-2429 phone: 33-1-42 04 29 25 fax: (216) 655-2176 fax: 33-1-45 06 46 99 annunciator output the annunciator output is a square wave running at the backplane frequency (for example, 167hz when f osc = 40khz). the peak-to-peak amplitude is equal to (v dd C v disp ). connecting an annunciator of the lcd to the annunciator output turns it on; connecting it to its backplane turns it off. lcd drive voltage (v disp ) the peak-to-peak lcd drive voltage is equal to (v dd C v disp ). in the 40-pin dual-in-line package (dip), v disp is internally connected to dgnd, providing a typical lcd drive voltage of 5v p-p . for applications with a wide temperature range, some lcds require that the drive levels vary with temperature to maintain good viewing angle and display contrast. in this case, the tc820 44-pin package provides a pin connection for v disp . figure 27 shows tc820 circuits that can be adjusted to give a temperature compensation of about 10mv/ c between v dd and v disp . the diode between gnd and v disp should have a low turn-on voltage because v disp cannot exceed 0.3v below gnd. crystal source two sources of the 40 khz crystal are: statek corp. spk electronics 512 n. main st. 2f-1, no. 312, sec. 4, orange, ca 92668 jen ai rd phone: (714) 639-7810 taipei, taiwan r.o.c. fax: (714) 997-1256 phone: (02) 754-2677 part #: cx-1v-40.0 fax: 886-2-708-4124 part#: qrt-38-40.0khz figure 26. typical tc820 lcd figure 25. typical display output waveforms high low over peak batt pin 1
3-170 telcom semiconductor, inc. 3-3/4 a/d converter with frequency counter and logic probe tc820 + v + v disp tc820 dgnd 24 39 12 11 200k w 39k w 5k w 75k w 1n4148 v v + v disp tc820 dgnd 24 39 v 12 11 39k w 20k w 2n2222 18k w note: pin numbers shown are for 44-pin flat package. tl071 1n5817 1n5817 figure 27. temperature-compensating circuits

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